1. Field of the Invention
The present invention relates to a semiconductor memory circuit, more particularly to a semiconductor memory which is provided with a bias circuit for a word line current discharging circuit and, further, to a semiconductor memory fabricated by saturation-type memory cells each comprised of bipolar transistors.
2. Description of the Prior Art
A typical semiconductor memory is comprised of a plurality of word lines, a plurality of bit lines, and a plurality of memory cells located at the intersection of the word lines and bit lines. Semiconductor memories utilize various types of memory cells. The present invention relates to a semiconductor memory utilizing saturation-type memory cells.
Generally, in such a semiconductor memory, that is, a static semiconductor memory, a so-called holding current flows through each memory cell so as to maintain the stored data of logical "1" or "0". When the memory cell is to be changed from a half selected state to a nonselected state, the hold current is discharged. The greater the discharged holding current, the faster the switching speed from the half selected state to the nonselected state. However, from the viewpoints of large memory capacity and low power consumption, the discharged holding current (I.sub.H) should preferably be small. Thus, it is difficult to increase the switching speed by making the hold current large. One previous proposal to get around this problem and achieve a fast switching speed is to have a discharging current (I.sub.D) selectively absorbed from a selected word line.
Also in such a semiconductor memory, the emitter voltage of a detection transistor in each half selection memory cell is usually raised to a high level to prevent write errors. However, when the emitter voltage is raised to a high level, part of the discharging current (I.sub.D) from the word lines is unnecessarily branched into the bit line connected to the detection transistor of each nonselection memory cell. This means that the discharging current (I.sub.D) varies in accordance with the amount of the current which is branched into the detection transistor. Accordingly, the desired constant amplitude of the discharging current (I.sub.D) cannot be maintained. This is because physical characteristics of the detection transistors obtained in one production lot are not always the same as those of the detection transistors obtained in another production lot.